What are the CLK (A) and CLK (B) SMA Clock Ports Used For?

Clock A and Clock B are External Reference Clock inputs, used by the test applications in Port 1 and Port 2, respectively.

On certain VeEX test sets, the 50 Ohms SMA(f) ports labeled CLK A (or CLK 1) and CLK B (or CLK 2) are independent External Clock inputs, used as frequency, phase or timing references by test applications in test Port 1 (P1) and Port 2 (P2) groups, respectively. For example, if you are running a Wander measurement with external reference clock, on any of the Port 2 test interfaces, the required reference clock must be connected to the CLK B SMA.

On VeEX TX340s multi-service test set, the CLK (A) external clock reference input is used by the test applications running in Port 1 and CLK (B) is for the applications in Port 2 of the same module (built-in modules are separated by a vertical orange line). Note that a TX300s test platform loaded with two TX340sm modules (four test port groups) will have two sets of clock reference inputs (total of four SMA CLK ports), with a pair of CLK ports dedicated to each module. (The ones on the left are for test Module 2. The ones on the center are for test Module 1.)
On the original RXT-6000e and RXT-6200 (1st Gen) test modules, the CLK (A) external clock reference input is used by the test application running in Port 1 and CLK (B) is for the application in Port 2.
On the RXT-6200+ (2nd Gen) test module, the CLK IN (1) external clock reference input is used by the test application running in Port 1 and CLK (2) is for the application in Port 2. This version is easily recognizable because it also has two SMA(f) clock output ports, CLK OUT (1) and CLK OUT (2), which follow the same logic. If fitted with the lower rate (legacy) TDM hardware option, there is a separate CLK IN (PDH) port dedicated to electrical SDH/SONET and PDH/DSn applications.
On the MTX150 test set, the CLK (A) is reserved for SDH/SONET/PDH/DSn electrical interfaces from 64 kbit/s to 155 Mbit/s. While CLK (B) is to be used for IEEE C37.94, SDH/SONET (optical) and SyncE applications up to 10 Gbit/s.

Supported External Reference Clock Formats

Depending on the test set and test application, the CLK and CLK IN SMA ports can support a variety of industry standard unbalanced clock signals (coaxial) for frequency and timing.

Frequency Sources: 1.544 MHz, 2.048 MHz, 10 MHz (square and sinusoidal, per ITU-T G.703, unbalanced, 50Ω)
Datalink Clocks: 64 kbit/s, 1.544 Mbit/s, 2.048 Mbit/s (bipolar AMI/B8ZS/HDB3)
Timing: 1PPS (per ITU-T G.703, unbalanced, 50Ω)

Balanced (symmetrical pair) clocks are not supported by the SMA ports (e.g., V.11, RS422). The use of external V.11-to-TTL/RS232 style adapters is not recommended for 1PPS clock sources, because the required electronics add (unknown) delay.

Test applications that use external reference clocks include:

Frequency synchronization for C37.94, SDH/SONET, PDH/DSn, SyncE and CPRI transmit side
Wander (TIE, MTIE, TDEV) Measurement for SDH/SONET, PDH/DSn, IEEE C37.94, SyncE and CPRI
Time Error measurements (phase error, TE) for 1PPS clocks and 1588v2/PTP
One Way Delay (legacy implementations)

The use of short flexible SMA-to-BNC adapter cables is recommended. In certain cases, rigid adapters may transfer undesired mechanical stress to the test set's connector panel.

What are the CLK (A) and CLK (B) SMA Clock Ports Used For?

Clock A and Clock B are External Reference Clock inputs, used by the test applications in Port 1 and Port 2, respectively.

Supported External Reference Clock Formats

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