Frequency Offset is the frequency difference between a network element port and the Primary Reference Clock (PRC). A Clock Slip occurs when the frequency difference causes the pulses of the device under test (DUT) to shift by one full cycle (period)
1. Frequency Offset (Clock Offset)
In Synchronous or Plesiochronous (almost synchronous) communication links, frequency offset is the frequency difference between a network element (NE) port ("slave") and the Primary clock reference (PRC) or "master" clock. Traditionally, frequency offset (inaccuracy or error) is given in parts-per-million (ppm), however, modern precision timing applications use parts-per-billion (ppb) or parts-per-trillion, to refer to the very small frequency differences expected.
- +1 ppm offset in a 2.048 MHz clock is +2.048 Hz or a total of 2,048,002.05 MHz
- -1 ppm offset in a 2.048 MHz clock is -2.048 Hz or a total of 2,047,997.95 MHz
It is expected that network elements shall recover the signal's clock coming from the core network and regenerate it in both directions (downstream and upstream) to maintain frequency synchronization. However, due to component failures or misconfiguration, a constant frequency difference (inaccuracy) between the PRC and the local clock causes the pulses to constantly slide in one direction with respect to a reference (accurate) clock. As the phase error accumulates, it can cause periodic clock slips, bit slips and even bit errors.
The simplified diagram below shows reference (master, PRC) clock pulses in green. The blue clock (or signal) pulses represent the output of a DUT out of synchronization (or free running) with a transmit frequency faster than the PRC. In this example, since the DUT is running faster, the rising edge of its pulses progressively appear earlier than the reference pulses, increasing the time interval error (TIE) between the two (red line or wander). A straight TIE or TE wander ramp is a clear indication of frequency offset between the DUT and the reference clock.
Frequency offset measurements require an accurate reference clock traceable to (in sync with) the PRC or by comparing two signals (using the highest hierarchy signal available as the reference). The reference is often the downstream signal, coming from the Core of the network.
Test sets offer two ways to measure Frequency Offset.
- The BER test often offers a simple way to compare clocks recovered from the transmission signal (T1, E1, SDH. SONET, Ethernet, etc.) measuring the differences between the DUT against the network's clock. This is often referred as Frequency Offset or Clock Offset and it gives results with resolution in fractions of parts-per-million (ppm). For practical reasons, his is enough to validate the proper configuration of traditional transmission links. Some simpler test sets may offer Clock Slips, that counts when the TIE surpasses the "width" of a bit.
- More advanced test sets offer more precise Clock Wander measurements. They measure Time Interval Error (TIE) or Time Error (TE) over a period of time and allows precise extraction of the clock offset information, with resolution in the order of fractions of parts-per-billion (ppb) or parts-per trillion. Often used for precision synchronous signals (e.g., SDH/SONET, SyncE, eCPRI, PTP, etc.)
1.1 Using External Reference Clock to Measure Frequency Offset
If there is access to an accurate and traceable reference clock signal (PRC, SSU, SEC, BITS/SETS) or access to GNSS/GPS, to synchronize the test set, this will give the most accurate frequency offset measurements.
In the measurement settings, configure the Measurement Reference Clock as External 10 MHz, 2.048 MHz, 2.048 Mbit/s, etc. Depending on the test set and test application, this external signal may be connected to the second BNC receiver (Rx2) or to a dedicated SMA CLK IN port.
A system in sync should give frequency offset measurements close to zero.
- For PDH/DSn, SDH/SONET or SyncE BERT test, this is usually shown as alternating between ±0.1 ppm.
- For precision measurements, the use of dedicated Wander Measurement Analysis is recommended, in order to measure frequency errors more accurately, below ppb.
1.2 Verifying Link Clock Recovery
For day-to-day applications, a relative clock measurement is a more practical way to verify that a remote network element (client or slave) is in sync with the network. That is, the DUT is properly configured to recover the clock from the network and use it to transmit its own signals in sync with the network, both downstream and upstream.
In the measurement settings, configure the Measurement Reference Clock as External 2.048 Mbit/s. Depending on the test set and test application, this external signal is connected to the second BNC receiver (Rx2) or to a dedicates SMA CLK IN port.
A system in sync should give frequency offset measurements close to zero. The allowed tolerances depend on the transmission technology and data rate, typically ranging from ±20 ppm to ±100 ppm thresholds. However, in modern systems the expected frequency offset should still be very close to zero ppm. The presence of frequency offsets > 0 ppm may indicate DUT misconfiguration or hardware failure.
1.3 Can the Internal Oscillator be Used as Reference?
No. Using the test set's internal quartz oscillator as a reference clock for frequency offset measurements may not be technically correct, because the test set is free running (not in sync with the network).
However, it is understood that communication service providers don't expect to have access to reference clocks at their customers' premises or remote sites. So, VeEX uses quartz oscillators with frequency accuracies better than ±3.5 ppm (typically ±1 ppm), so it can be used to provide a fairly good indication of whether the link or device under test is recovering the clock correctly. This approach may only apply to non-precision timing applications.
In this case, users should look for stable frequency offsets <±5 ppm.
2. Clock Slips
A Clock Slip, sometimes also referred as Bit Slip, occurs when the frequency offset causes the pulses of the device under test (DUT) to wander up to a full cycle or bit width (gains or loses one full cycle compared to the reference). Going back to the simple diagram, if the relative phase difference between the blue and green signals continue to increase, their phases will eventually align again. At that point, they are not back in sync! They have accumulated a 1-cycle difference or Clock Slip. As time goes by, the clock slips will continue to accumulate and be counted by the test set.
For example, if we use a 2,048,000 bit/s reference clock, to run a test on a 2.048 Mbit/s link with +0.1 ppm frequency offset (≈2,048,000.2 Mbit/s), the phase between the two will drift a rate of 0.2 μs/s (or 204.8ns every second). Taking into account that an E1 bit period is ≈488ns, it will take about 2.38 seconds for a Clock Slip to occur. If the frequencies are constant, the Clock Slip counter will be increased by one every 2.38 seconds. If the DUT's frequency varies over time, slower frequencies generate negative clock slips that are subtracted from the counter. In general, in a well synchronized field equipment, the average clock slip counter should stay around zero.
Clock Slips or Bit Slips are considered a legacy measurement (still requested by certain traditional customers). Modern communication systems have robust clock recovery systems and buffers that allow them to run error free, even in the presences of relatively high Frequency Offsets and their resulting Clock Slips. It is recommended to focus on Frequency Offset and Bit Errors instead.
If a free-running test set reference is being used to perform the test, the Clock Slip counter should be ignored, as it will be counting up or down at all times.